1. Field of the Invention
The present invention relates to an internal synchronous type of static RAM (random access memory) (the static RAM will be called "SRAM" in the specification), and more specifically to an internal synchronous SRAM having a precharge circuit and a pull-down circuit.
2. Description of Related Art
In general, the internal synchronous SRAM comprises an SRAM cell array having a number of SRAM cells arranged in the form of a matrix, a plurality of row or word lines and a plurality of pairs of column or bit lines. One SRAM cell is located at each intersection between each word line and each pair of bit lines. A precharge circuit is connected to all the bit lines so as to precharge the bit lines. In addition, a selector is connected to all the bit lines so as to connect only a selected pair of bit lines to a common data bus. A pull-down circuit is connected to the common data bus.
In operation, before data is read from or written into a selected SRAM cell, the bit lines are precharged by means of the precharge circuit, and at the same time, the common data bus is pulled down by the pull-down circuit. In the case that a voltage supply voltage varies, the common data bus is often maintained at a high potential which prevents turn-on of the selector. The pull-down circuit is provided to prevent the common data bus from being maintained at a high potential which prevents turn-on of the selector, regardless of variation of a voltage supply voltage. However, since the common data bus is connected to the bit lines through the selector, if the voltage supply voltage does not vary almost, the bit lines is caused to drop to a level further lower than a level sufficient to permit a quick turn-on of the selector. This excessive drop of the bit line potential is apt to break the data of the SRAM cells. This is contrary to the object of the precharge, namely the prevention of break of data stored in SRAM cells.
In general, if the potential of the bit lines drops to a half or less of a voltage supply voltage, the data of the SRAM cells is easily broken. This inclination becomes remarkable in the case that the voltage supply voltage itself is low.